This invention relates to a data processor, such as a digital computer, which processes macroinstructions in an overlapped fashion. More particularly, it relates to a data processor which is constructed so as to permit data to be aligned and selected.
In conventional digital computers, a macroinstruction to be subsequently executed is read out from a memory which stores macroinstructions and data therein, an address for specifying data (hereinbelow, termed the "storage operand") for use in the execution of the particular macroinstruction is obtained from the macroinstruction by means of an instruction unit, the corresponding storage operand is read out from the memory on the basis of the storage operand address, and the particular macroinstruction is executed. In this case, the storage operand which is read out from the memory by one readout operation has a fixed length peculiar to the processor, for example, 8 bytes. Further, it is common practice that the readout of the storage operand from the memory cannot be made on a storage operand of 8 bytes beginning from an arbitrary address position, but that it is made on block data having the length of 8 bytes from a predetermined boundary position between blocks of 8 bytes. Accordingly, in the case where the storage operand desired to be read out is data located on both sides of the boundary position, two readout operations for reading out from the memory 8 bytes having an address smaller than the particular boundary position and 8 bytes having an address greater than the same boundary position are carried out even if the storage operand wished for is shorter than 8 bytes. Thereafter, using an arithmetic and logic unit, the two 8-byte data blocks are aligned so as to permit the desired data of 8 bytes to be selected therefrom. Since in this manner, the conventional processor performs the alignment of data and the selection of data with use of an arithmetic and logic unit, it requires a long processing time. This results in an increase in the processing time of an instruction. In order to eliminate such a disadvantage, data processors in which the alignment of data is effected by a circuit used exclusively for alignment (hereinbelow, called an "align circuit") have been proposed in the following literatures:
1. Specification of Japanese Published Unexamined Patent Application No. 49-95546
2. Specification of Japanese Published Unexamined Patent Application No. 53-94133
In the former, data of 8 bytes including desired data of 4 bytes is read out from a memory, the 8-byte data read out is aligned by the use of a data aligner, and the desired 4-byte data is thereafter selected. Further, in the latter system, data of 16 bytes including desired data of a length within 8 bytes is aligned with a data aligner, whereupon the desired data having the length within 8 bytes is selected.
When the arbitrary alignment of data is made with the data aligner in this way, the processing time of an instruction can be shortened. However, in order to perform the alignment of data during the execution of any of various instructions, the control circuit for the data aligner becomes extremely complicated. In particular, the timing and procedure in which the alignment of data is carried out differ depending upon individual instructions. Accordingly, the control circuit must be constructed so that, for each instruction, the desired operation can be performed at a predetermined timing in the course of the execution of the instruction.
To the end of solving such problem, a technique in which the alignment of data is effected by the use of a microinstruction has been previously proposed and this technique is disclosed in our U.S. Pat. No. 4,317,170, issued on February 23, 1982. According to this technique, the alignment of data can be performed for all macroinstructions by means of a simple device using microinstructions. However, in the case where it is intended to actually apply this technique to a large-sized computer, there occurs the problem that the processing speed of the macroinstruction lowers due to the use of the microinstructions. Especially in the large-sized computer, the respective macroinstructions are executed in an overlapped manner by a so-called pipeline type advanced control system. More specifically, in such a system the execution of each macroinstruction is divided into a plurality of stages, for example, the four stages of:
(1) D-stage of decoding the macroinstruction and calculating an operand address necessary for the execution of the instruction,
(2) A-stage of converting the calculated operand address into a physical address,
(3) L-stage of reading out a corresponding operand from a memory by the use of the converted physical operand address, and
(4) E-stage of executing an operation with regard to the operand.
Each of the stages from the D-stage to the L-stage is processed within one machine cycle, and the stages of each macroinstruction are processed in parallel with different stages of the other macroinstructions. Among the various stages, the E-stage is controlled by microinstruction. On the other hand, the remaining D-, A- and L-stages are controlled by wired logic circuits designed for that exclusive use.
Accordingly, if the alignment control technique employing microinstructions as previously proposed is introduced into such a conventional system, the stage control circuits for the D-, A- and L-stages must be drastically altered. On the other hand, some of the macroinstructions require storage operands, not only in the L-stages, but also in the E-stages. In the processings of such macroinstructions, accordingly, if the alignment control of the storage operand read out in the E-stage is effected by means of a wired logic circuit which is designed for that exclusive use, the circuit therefor becomes complicated.
In this manner, when the large-sized computer which processes the macroinstructions in the overlapped fashion is provided with the data aligner, the system is inevitably rendered complicated.